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mos integrated circuit pd703130 v850e/ms2 tm 32-bit single-chip microcontroller document no. u15390ej1v0ds00 (1st edition) date published april 2001 n cp(k) printed in japan preliminary data sheet the pd703130 is a member of the v850 family tm of 32-bit single-chip microcontrollers designed for real-time control operations. these microcontrollers provide on-chip features, including a 32-bit cpu, ram, interrupt controller, real-time pulse unit, serial interface, a/d converter, and dma controller. the pd703130 is a romless version product. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. v850e/ms2 user?s manual hardware: u14985e v850e/ms1 tm user?s manual architecture: u12197e features ? number of instructions: 81 ? minimum instruction execution time 30 ns (@ 33 mhz operation) ? general-purpose registers 32 bits 32 ? instruction set suitable for control applications ? internal memory rom: none ram: 4 kb ? advanced on-chip interrupt controller ? real-time pulse unit suitable for control operations ? powerful serial interface (on-chip dedicated baud rate generator) ? on-chip clock generator ? 10-bit resolution a/d converter: 4 channels ? dma controller: 4 channels ? power saving functions applications ? optical storage equipment (dvd players, etc.) ? system control for digital consumer equipment, etc. ? 2001 the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information.
preliminary data sheet u15390ej1v0ds 2 pd703130 ordering information part number package maximum operating frequency internal rom pd703130gc-8eu 100-pin plastic lqfp (fine pitch) (14 14) 33 mhz none pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) ? pd703130gc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 d1 d0 v dd intp103/dmarq3/p07 intp102/dmarq2/p06 intp101/dmarq1/p05 intp100/dmarq0/p04 tclr10/p02 to100/p00 v ss intp113/dmaak3/p17 intp112/dmaak2/p16 intp111/dmaak1/p15 intp110/dmaak0/p14 tclr11/p12 to110/p10 tclr12/p102 to120/p100 ani3/p73 ani2/p72 ani1/p71 ani0/p70 av dd av ss av ref a8 a9 a10 a11 a12 a13 a14 a15 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 hv dd cs0/p80 cs3/ras3/p83 cs4/ras4/iowr/p84 cs5/ras5/iord/p85 lcas/lwr/p90 ucas/uwr/p91 rd/p92 we/p93 nmi/p20 txd0/so0/p22 rxd0/si0/p23 sck0/p24 txd1/so1/p25 rxd1/si1/p26 sck1/p27 v dd intp130/p34 ti13/p33 cv dd x2 x1 cv ss cksel mode0 mode2 reset v ss clkout/px7 wait/px6 hldrq/p97 hldak/p96 oe/p95 bcyst/p94 d2 d3 d4 d5 d6 d7 v ss d8/p50 d9/p51 d10/p52 d11/p53 d12/p54 d13/p55 d14/p56 d15/p57 hv dd a0 a1 a2 a3 a4 a5 a6 a7 v ss 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
preliminary data sheet u15390ej1v0ds 3 pd703130 pin names a0 to a23: address bus p20, p22 to p27: port 2 ani0 to ani3: analog input p33, p34: port 3 av dd : analog power supply p50 to p57: port 5 av ref : analog reference voltage p60 to p67: port 6 av ss : analog ground p70 to p73: port 7 bcyst: bus cycle start timing p80, p83 to p85: port 8 cksel : clock generator operating mode select p90 to p97: port 9 clkout: clock output p100, p102: port 10 cs0, cs3 to cs5: chip select px6, px7: port x cv dd : clock generator power supply ras3 to ras5: row address strobe cv ss : clock generator ground rd: read d0 to d15: data bus reset: reset dmaak0 to dmaak3 : dma acknowledge rxd0, rxd1: receive data dmarq0 to dmarq3 : dma request sck0, sck1: serial clock hldak: hold acknowledge si0, si1: serial input hldrq: hold request so0, so1: serial output hv dd : power supply for external pins tclr10 to tclr12: timer clear intp100 to intp103, : interrupt request from peripherals ti13: timer input intp110 to intp113, to100, to110: timer output intp130 to120 iord: i/o read strobe txd0, txd1: transmit data iowr: i/o write strobe ucas: upper column address strobe lcas: lower column address strobe uwr: upper write strobe lwr: lower write strobe v dd : power supply for internal unit mode0, mode2: mode v ss : ground nmi: non-maskable interrupt request wait: wait oe: output enable we: write enable p00, p02, p04 to p07: port 0 x1, x2: crystal p10, p12, p14 to p17: port 1
preliminary data sheet u15390ej1v0ds 4 pd703130 internal block diagram hldrq hldak cs0,cs3 to cs5 ras3 to ras5 iowr iord bcyst we rd oe uwr/ucas lwr/lcas wait a0 to a23 d0 to d15 dmarq0 to dmarq3 dmaak0 to dmaak3 nmi to100,to110, to120 intp100 to intp103 intp110 to intp113 intp130 tclr10 to tclr12 ti13 intc rpu sio ram 4 kb cpu pc instruction queue system registers general-purpose registers (32 bits 32) alu multiplier (32 32 64) barrel shifter port px6,px7 p100,p102 p90 to p97 p80,p83 to p85 p70 to p73 p60 to p67 p50 to p57 p33,p34 p22 to p27 p20 p10,p12,p14 to p17 p00,p02,p04 to p07 hv dd cg system controller bcu clkout cksel x1 x2 cv dd cv ss mode0,mode2 reset uart0/csi0 brg0 uart1/csi1 brg1 adc so0/txd0 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 ani0 to ani3 av ref av ss av dd v dd v ss dmac pagerom controller dramc
preliminary data sheet u15390ej1v0ds 5 pd703130 contents 1. differences between v850e/ms2 and v850e/ms1............................................................ 6 2. pin functions ............................................................................................................... .............. 7 2.1 port pins ................................................................................................................... .............. 7 2.2 non-port pins ............................................................................................................... .......... 9 2.3 pin i/o circuits and recommended connection of unused pins..................................... 11 3. electrical specifications ................................................................................................... 14 4. package drawing ............................................................................................................. ........ 68 5. recommended soldering conditions ............................................................................. 69
preliminary data sheet u15390ej1v0ds 6 pd703130 1. differences between v850e/ms2 and v850e/ms1 product name v850e/ms2 v850e/ms1 item pd703130 pd703100-33 pd703102-33 internal rom none none 128 kb (mask rom) maximum operating frequency 33 mhz 33 mhz memory space 64 mb linear (only 22 mb supports on-chip cs signal) 64 mb linear chip select output 4 spaces 8 spaces interrupt function external: 10, internal: 35 external: 25, internal: 47 i/o lines input: 5, i/o: 52 input: 9, i/o: 114 timer 16-bit timer/event counter: 4 channels 16-bit timer: 2 channels 16-bit timer/event counter: 6 channels 16-bit timer: 2 channels serial interface csi/uart: 2 channels dedicated baud rate generator: 2 channels csi: 2 channels csi/uart: 2 channels dedicated baud rate generator: 3 channels a/d converter 10-bit resolution 4 channels 10-bit resolution 8 channels package 100-pin plastic lqfp (fine-pitch) (14 14) 144-pin plastic lqfp (fine-pitch) (20 20) other noise tolerance and noise radiation will differ due to differences in circuit scale and mask layout.
preliminary data sheet u15390ej1v0ds 7 pd703130 2. pin functions 2.1 port pins (1/2) pin name i/o function alternate function p00 to100 p02 tclr10 p04 intp100/dmarq0 p05 intp101/dmarq1 p06 intp102/dmarq2 p07 i/o port 0 6-bit i/o port input/output can be specified in 1-bit units. intp103/dmarq3 p10 to110 p12 tclr11 p14 intp110/dmaak0 p15 intp111/dmaak1 p16 intp112/dmaak2 p17 i/o port 1 6-bit i/o port input/output can be specified in 1-bit units. intp113/dmaak3 p20 input nmi p22 txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 i/o port 2 p20 is an input only port. when a valid edge is input, this pin operates as nmi input. also, bit 0 of the p2 register indicates the nmi input status. p22 to p27 are 6-bit i/o port. input/output can be specified in 1-bit units. sck1 p33 ti13 p34 i/o port 3 2-bit i/o port input/output can be specified in 1-bit units. intp130 p50 to p57 i/o port 5 8-bit i/o port input/output can be specified in 1-bit units. d8 to d15 p60 to p67 i/o port 6 8-bit i/o port input/output can be specified in 1-bit units. a16 to a23 p70 to p73 input port 7 4-bit input only port ani0 to ani3 p80 cs0 p83 cs3/ras3 p84 cs4/ras4/iowr p85 i/o port 8 4-bit i/o port input/output can be specified in 1-bit units. cs5/ras5/iord
preliminary data sheet u15390ej1v0ds 8 pd703130 (2/2) pin name i/o function alternate function p90 lcas/lwr p91 ucas/uwr p92 rd p93 we p94 bcyst p95 oe p96 hldak p97 i/o port 9 8-bit i/o port input/output can be specified in 1-bit units. hldrq p100 to120 p102 i/o port 10 2-bit i/o port input/output can be specified in 1-bit units. tclr12 px6 wait px7 i/o port x 2-bit i/o port input/output can be specified in 1-bit units. clkout
preliminary data sheet u15390ej1v0ds 9 pd703130 2.2 non-port pins (1/2) pin name i/o function alternate function to100 p00 to110 p10 to120 output pulse signal output for timers 10 to 12 p100 tclr10 p02 tclr11 p12 tclr12 input external clear signal input for timers 10 to 12 p102 ti13 input external count clock input for timer 13 p33 intp100 p04/dmarq0 intp101 p05/dmarq1 intp102 p06/dmarq2 intp103 input external maskable interrupt request input, shared as external capture trigger input for timer 10 p07/dmarq3 intp110 p14/dmaak0 intp111 p15/dmaak1 intp112 p16/dmaak2 intp113 input external maskable interrupt request input, shared as external capture trigger input for timer 11 p17/dmaak3 intp130 input external maskable interrupt request input, shared as external capture trigger input for timer 13 p34 so0 p22/txd0 so1 output serial transmit data output (3-wire) for csi0 and csi1 p25/txd1 si0 p23/rxd0 si1 input serial receive data input (3-wire) for csi0 and csi1 p26/rxd1 sck0 p24 sck1 i/o serial clock i/o (3-wire) for csi0 and csi1 p27 txd0 p22/so0 txd1 output serial transmit data output for uart0 and uart1 p25/so1 rxd0 p23/si0 rxd1 input serial receive data input for uart0 and uart1 p26/si1 d0 to d7 ? d8 to d15 i/o 16-bit data bus for external memory p50 to p57 a0 to a15 ? a16 to a23 output 24-bit address bus for external memory p60 to p67 lwr output lower byte write-enable signal output for external data bus p90/lcas uwr output higher byte write-enable signal output for external data bus p91/ucas rd output read strobe signal output for external data bus p92 we output write enable signal output for dram p93 oe output output enable signal output for dram p95
preliminary data sheet u15390ej1v0ds 10 pd703130 (2/2) pin name i/o function alternate function lcas output column address strobe signal output for dram?s lower data p90/lwr ucas output column address strobe signal output for dram?s higher data p91/uwr ras3 p83/cs3 ras4 p84/cs4/iowr ras5 output row address strobe signal output for dram p85/cs5/iord bcyst output strobe signal output indicating start of bus cycle p94 cs0 p80 cs3 p83/ras3 cs4 p84/ras4/iowr cs5 output chip select signal output p85/ras5/iord wait input control signal input for inserting waits in bus cycle px6 iowr output dma write strobe signal output p84/ras4/cs4 iord output dma read strobe signal output p85/ras5/cs5 dmarq0 to dmarq3 input dma request signal input p04/intp100 to p07/intp103 dmaak0 to dmaak3 output dma acknowledge signal output p14/intp110 to p17/intp113 hldak output bus hold acknowledge output p96 hldrq input bus hold request input p97 ani0 to ani3 input analog input to a/d converter p70 to p73 nmi input non-maskable interrupt request input p20 clkout output system clock output px7 cksel input input for specifying clock generator?s operation mode ? mode0, mode2 input specify operation modes ? reset input system reset input ? x1 input ? x2 ? connecting resonator for system clock. input is via x1 when using an external clock. ? av ref input reference voltage input for a/d converter ? av dd ? positive power supply for a/d converter ? av ss ? ground potential for a/d converter ? cv dd ? positive power supply for dedicated clock generator ? cv ss ? ground potential for dedicated clock generator ? v dd ? positive power supply (power supply for internal units) ? hv dd ? positive power supply (power supply for external pins) ? v ss ? ground potential ?
preliminary data sheet u15390ej1v0ds 11 pd703130 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the i/o circuit type of each pin and recommended connection of unused pins. figure 2-1 shows the various circuit types using partially abridged diagrams. when connecting to v dd or v ss via a resistor, a resistance value in the range of 1 to 10 k ? is recommended. table 2-1. i/o circuit type of each pin and recommended connection of unused pins (1/2) pin i/o circuit type recommended connection of unused pins p00/to100 p02/tclr10 p04/intp100/dmarq0 to p07/intp103/dmarq3 p10/to110 p12/tclr11 p14/intp110/dmaak0 to p17/intp113/dmaak3 5 input: independently connect to hv dd or v ss via a resistor output: leave open p20/nmi 2 connect directly to v ss p22/txd0/so0 p23/rxd0/si0 p24/sck0 p25/txd1/so1 p26/rxd1/si1 p27/sck1 p33/ti13 p34/intp130 p50/d8 to p57/d15 p60/a16 to p67/a23 5 input: independently connect to hv dd or v ss via a resistor output: leave open p70/ani0 to p73/ani3 9 connect directly to v ss p80/cs0, to p83/cs3/ras3 p84/cs4/ras4/iowr, p85/cs5/ras5/iord p90/lcas/lwr p91/ucas/uwr p92/rd p93/we p94/bcyst p95/oe p96/hldak p97/hldrq p100/to120 p102/tclr12 5 input: independently connect to hv dd or v ss via a resistor output: leave open
preliminary data sheet u15390ej1v0ds 12 pd703130 table 2-1. i/o circuit type of each pin and recommended connection of unused pins (2/2) pin i/o circuit type recommended connection of unused pins px6/wait px7/clkout 5 input: independently connect to hv dd or v ss via a resistor output: leave open a0 to a15 4 d0 to d7 5 cksel 1 reset mode0, mode2 2 ? av ref , av ss ? connect directly to v ss av dd ? connect directly to hv dd
preliminary data sheet u15390ej1v0ds 13 pd703130 figure 2-1. pin i/o circuits in p-ch v dd n-ch in data p-ch v dd n-ch in/out output disable input enable in + ? input enable p-ch n-ch v ref (threshold voltage) type 1 type 2 type 5 type 9 comparator schmitt-triggered input with hysteresis characteristics type 4 p-ch n-ch v dd out data output disable push-pull output with possible high-impedance output (p-ch, n-ch both off) caution replace v dd by hv dd when referencing the circuit diagrams shown above.
preliminary data sheet u15390ej1v0ds 14 pd703130 3. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit v dd v dd pin ? 0.5 to +4.6 v hv dd hv dd pin, hv dd v dd ? 0.5 to +7.0 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd av dd pin ? 0.5 to hv dd + 0.5 note v power supply voltage av ss av ss pin ? 0.5 to +0.5 v input voltage v i except x1 pin ? 0.5 to hv dd + 0.5 note v clock input voltage v k x1, v dd = 3.0 to 3.6 v ? 0.5 to v dd + 1.0 note v 1 pin 4.0 ma output current, low i ol total of all pins 100 ma 1 pin ? 4.0 ma output current, high i oh total of all pins ? 100 ma output voltage v o hv dd = 5.0 v 10% ? 0.5 to hv dd + 0.5 note v av dd > hv dd ? 0.5 to hv dd + 0.5 note v analog input voltage v ian p70/ani0 to p73 pins hv dd av dd ? 0.5 to av dd + 0.5 note v av dd > hv dd ? 0.5 to hv dd + 0.5 note v a/d converter reference input voltage av ref hv dd av dd ? 0.5 to av dd + 0.5 note v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 60 to +150 c note be sure not to exceed the absolute maximum ratings (max. value) of the each power supply voltage. cautions 1. do not make direct connections of the output (or input/output) pins of the ic product with each other, and also avoid direct connections to v dd , v cc , or gnd. however, the open drain pins or the open collector pins can be directly connected to each other. a direct connection can also be made for an external circuit designed with timing specifications that prevent conflicting output from pins subject to a high-impedance state. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance.
preliminary data sheet u15390ej1v0ds 15 pd703130 capacitance (t a = 25 c, v dd = hv dd = cv dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions operation mode internal operating clock frequency (f x ) operating ambient temperature (t a ) power supply voltage (v dd , hv dd ) direct mode 10 to 33 mhz note 1 ? 40 to +85 c pll mode note 2 20 to 33 mhz note 3 ? 40 to +85 c v dd = 3.0 to 3.6 v, hv dd = 5.0 v 10% notes 1. set the input clock frequency used in direct mode to 20 to 66 mhz. 2. the internal operating clock frequency in pll mode is the value for 5 operation. when used for 1 or 1/2 operation as set by the ckdivn (n = 0, 1) bit of the ckc register, operation at a frequency of 20 mhz or less is possible. 3. set the input clock frequency used in pll mode to 4.0 to 6.6 mhz.
preliminary data sheet u15390ej1v0ds 16 pd703130 recommended oscillator (a) ceramic resonator (i) murata mfg. co., ltd. (t a = ? ? ? ? 40 to +85 c) recommended circuit constant oscillation voltage range manu- facturer part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) csts400mg06 note (cstls4m00g56-b0) 4.0 on-chip on-chip 0 3.0 3.6 0.6 cstcr4m00g55-r0 4.0 on-chip on-chip 0 3.0 3.6 0.6 csts0500mg06 note (cstls5m00g56-b0) 5.0 on-chip on-chip 0 3.0 3.6 0.6 cstcr5m00g55-r0 5.0 on-chip on-chip 0 3.0 3.6 0.6 csts066mg06 note (cstls6m60g56-b0) 6.6 on-chip on-chip 0 3.0 3.6 0.6 murata mfg. cstcr6m60g55-r0 6.6 on-chip on-chip 0 3.0 3.6 0.6 note the part number will be changed to the part number in the parentheses from june 2001. cautions 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area enclosed by broken lines. 3. sufficiently evaluate the matching between the pd703130 and the resonator. x1 c1 x2 c2 r d
preliminary data sheet u15390ej1v0ds 17 pd703130 (ii) tdk (t a = ? ? ? ? 40 to +85 c) recommended circuit constant oscillation voltage range manu- facturer part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) fcr4.0mc5 4.0 on-chip on-chip 0 3.0 3.6 0.73 fcr5.0mc5 5.0 on-chip on-chip 0 3.0 3.6 0.68 tdk fcr6.0mc5 6.0 on-chip on-chip 0 3.0 3.6 0.58 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area enclosed by broken lines. 3. sufficiently evaluate the matching between the pd703130 and the resonator. (iii) kyocera corporation (t a = ? ? ? ? 20 to +80 c) recommended circuit constant oscillation voltage range type part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) kbr-4.0mkc 4.0 on-chip on-chip 0 3.0 3.6 0.80 kbr-5.0mkc 5.0 on-chip on-chip 0 3.0 3.6 0.70 lead kbr-6.0mkc 6.0 on-chip on-chip 0 3.0 3.6 0.76 pbrc4.00hr 4.0 on-chip on-chip 0 3.0 3.6 0.80 pbrc5.00hr 5.0 on-chip on-chip 0 3.0 3.6 0.70 smd pbrc6.00hr 6.0 on-chip on-chip 0 3.0 3.6 0.76 cautions 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area enclosed by broken lines. 3. sufficiently evaluate the matching between the pd703130 and the resonator. x1 c1 x2 c2 r d x1 c1 x2 c2 r d
preliminary data sheet u15390ej1v0ds 18 pd703130 (b) external clock input (t a = ?40 to +85 c) x1 x2 open external clock caution input cmos-level voltage to the x1 pin.
preliminary data sheet u15390ej1v0ds 19 pd703130 dc characteristics (t a = ?40 to +85 c, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 10%, v ss = 0 v) parameter symbol condition min. typ. max. unit except note 1 2.2 hv dd + 0.3 v input voltage, high v ih note 1 0.8hv dd hv dd + 0.3 v except note 1 and note 2 ? 0.5 +0.8 v input voltage, low v il note 1 ? 0.5 0.2hv dd v clock input voltage, high v xh x1 pin 0.8v dd v dd + 0.3 v clock input voltage, low v xl x1 pin ? 0.3 0.15v dd v hv t + note 1 , rising edge 3.0 v schmitt-triggered input threshold voltage hv t ? note 1 , falling edge 2.0 v i oh = ? 2.5 ma 0.7hv dd v output voltage, high v oh i oh = ? 100 ahv dd ? 0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = hv dd , except note 2 10 a input leakage current, low i lil v i = 0 v, except note 2 ? 10 a output leakage current, high i loh v o = hv dd 10 a output leakage current, low i lol v o = 0 v ? 10 a v dd + cv dd 2.0 fx 3.0 fx ma normal mode i dd1 hv dd 1.5 fx 2.5 fx ma v dd + cv dd 1.4 fx 1.8 fx ma halt mode i dd2 hv dd 0.7 fx 1.2 fx ma v dd + cv dd 1.4 2.5 ma idle mode i dd3 hv dd 20 100 a v dd + cv dd 20 100 a power supply current stop mode i dd4 hv dd 10 50 a notes 1. p20/nmi, mode0, mode2, cksel, reset 2. when the p70/ani0 to p73/ani3 pins are used as analog input. remarks 1. typ. values are reference values for when t a = 25c, v dd = cv dd = 3.3 v, and hv dd = 5.0 v. 2. direct mode: f x = 10 to 33 mhz pll mode: f x = 20 to 33 mhz 3. the unit for f x is mhz.
preliminary data sheet u15390ej1v0ds 20 pd703130 data hold characteristics (t a = ?40 to +85 c) parameter symbol condition min. typ. max. unit v dddr stop mode, v dd = v dddr 1.5 3.6 v data hold voltage hv dddr stop mode, hv dd = hv dddr v dddr 5.5 v data hold current i dddr v dd = v dddr 30 150 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time (from stop mode setting) t hvd 0ms stop mode release signal input time t drel 0ns data hold input voltage, high v ihdr p20/nmi, mode0, mode2, cksel, reset 0.8hv dddr hv dddr v data hold input voltage, low v ildr p20/nmi, mode0, mode2, cksel, reset 00.2hv dddr v remark typ. values are reference values for when t a = 25 c. hv dd reset (input) v ihdr v ihdr v ildr v dd t hvd t fvd v dddr t rvd t drel stop mode setting nmi (input) (released by falling edge) nmi (input) (released by rising edge) 3.0 v
preliminary data sheet u15390ej1v0ds 21 pd703130 ac characteristics (t a = ?40 to +85 c, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 10%, v ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input test points (a) p20/nmi, mode0, mode2, cksel, reset hv dd 0 v 0.8hv dd 0.2hv dd 0.8hv dd 0.2hv dd test points input signal (b) pins other than those listed in (a) above 2.4 v 0.4 v 2.2 v 0.8 v 2.2 v 0.8 v test points input signal ac test output test points load condition caution in cases where the load capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other element to reduce the device's load capacitance 50 pf. 2.4 v 0.8 v 2.4 v 0.8 v test points output signal c l = 50 pf dut (device under test)
preliminary data sheet u15390ej1v0ds 22 pd703130 (1) clock timing parameter symbol condition min. max. unit direct mode 15 50 ns x1 input cycle <1> t cyx pll mode 150 250 ns direct mode 5 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 5 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns x1 input fall time <5> t xf direct mode 4 ns pll mode 10 ns clkout output cycle <6> t cyk 30 100 ns clkout high-level width <7> t wkh 0.5t ? 7 ns clkout low-level width <8> t wkl 0.5t ? 4 ns clkout rise time <9> t kr 5ns clkout fall time <10> t kf 5ns remark t = t cyk <4> <5> <2> <3> <1> x1 (pll mode) <1> <2> <3> <4> <5> <9> <10> <7> <8> <6> x1 (direct mode) clkout (output)
preliminary data sheet u15390ej1v0ds 23 pd703130 (2) output waveform (other than x1, clkout) parameter symbol condition min. max. unit output rise time <12> t or 10 ns output fall time <13> t of 10 ns <13> signals other than x1, clkout <12> (3) reset timing parameter symbol condition min. max. unit reset high-level width <14> t wrsh 500 ns when power supply is on, and stop mode has been released 500 + t os ns reset low-level width <15> t wrsl other than when power supply is on, and stop mode has been released 500 ns remark t os : oscillation stabilization time <14> <15> reset (input)
preliminary data sheet u15390ej1v0ds 24 pd703130 (4) sram, external rom, or external i/o access timing (a) access timing (sram, external rom, or external i/o) (1/2) parameter symbol condition min. max. unit address, csn output delay time (from clkout ) <16> t dka 210ns address, csn output hold time (from clkout ) <17> t hka 210ns rd, iord delay time (from clkout ) <18> t dkrdl 214ns rd, iord delay time (from clkout ) <19> t hkrdh 214ns uwr, lwr, iowr delay time (from clkout ) <20> t dkwrl 210ns uwr, lwr, iowr delay time (from clkout ) <21> t hkwrh 210ns bcyst delay time (from clkout ) <22> t dkbsl 210ns bcyst delay time (from clkout ) <23> t hkbsh 210ns wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout ) <26> t skid 18 ns data input hold time (from clkout ) <27> t hkid 2ns data output delay time (from clkout ) <28> t dkod 210ns data output hold time (from clkout ) <29> t hkod 210ns remarks 1. maintain at least one of the data input hold times t hkid and t hrdid . 2. n = 0, 3 to 5
preliminary data sheet u15390ej1v0ds 25 pd703130 (a) access timing (sram, external rom, or external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0, 3 to 5 clkout (output) a0 to a23 (output) csn (output) bcyst (output) rd, iord (output) [read time] uwr, lwr, iowr (output) [write time] d0 to d15 (i/o) [read time] d0 to d15 (i/o) [write time] wait (input) <16> <17> <22> <23> <18> <19> <20> <21> <26> <27> <28> <29> <24> <25> <24> <25> t1 tw t2
preliminary data sheet u15390ej1v0ds 26 pd703130 (b) read timing (sram, external rom, or external i/o) (1/2) parameter symbol condition min. max. unit data input setup time (to address) <30> t said (1.5 + w d + w)t ? 28 ns data input setup time (to rd) <31> t srdid (1 + w d + w)t ? 32 ns rd, iord low-level width <32> t wrdl (1 + w d + w)t ? 10 ns rd, iord high-level width <33> t wrdh t ? 10 ns delay time from address, csn to rd, iord <34> t dard 0.5t ? 10 ns delay time from rd, iord to address <35> t drda (0.5 + i)t ? 10 ns data input hold time (from rd, iord ) <36> t hrdid 0ns delay time from rd, iord to data output <37> t drdod (0.5 + i)t ? 10 ns wait setup time (to address) <38> t saw note t ? 25 ns wait setup time (to bcyst ) <39> t sbsw note t ? 25 ns wait hold time (from bcyst ) <40> t hbsw note 0ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. i: the number of idle states that are inserted when a write cycle follows a read cycle. 5. maintain at least one of the data input hold times, t hkid or t hrdid . 6. n = 0, 3 to 5
preliminary data sheet u15390ej1v0ds 27 pd703130 (b) read timing (sram, external rom, or external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0, 3 to 5 uwr, lwr, iowr (output) rd, iord (output) d0 to d15 (i/o) t1 tw t2 clkout (output) <33> <32> <35> <38> <34> <31> <30> <36> <37> <39> <40> a0 to a23 (output) csn (output) wait (input) bcyst (output)
preliminary data sheet u15390ej1v0ds 28 pd703130 (c) write timing (sram, external rom, or external i/o) (1/2) parameter symbol condition min. max. unit wait setup time (to address) <38> t saw note t ? 25 ns wait setup time (to bcyst ) <39> t sbsw note t ? 25 ns wait hold time (from bcyst ) <40> t hbsw note 0ns delay time from address, csn to uwr, lwr, iowr <41> t dawr 0.5t ? 10 ns address setup time (to uwr, lwr, iowr ) <42> t sawr (1.5 + w d + w)t ? 10 ns delay time from uwr, lwr, iowr to address <43> t dwra 0.5t ? 10 ns uwr, lwr, iowr high-level width <44> t wwrh t ? 10 ns uwr, lwr, iowr low-level width <45> t wwrl (1 + w d + w)t ? 10 ns data output setup time (to uwr, lwr, iowr ) <46> t sodwr (1.5 + w d + w)t ? 10 ns data output hold time (from uwr, lwr, iowr ) <47> t hwrod 0.5t ? 10 ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. n = 0, 3 to 5
preliminary data sheet u15390ej1v0ds 29 pd703130 (c) write timing (sram, external rom, or external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0, 3 to 5 t1 tw t2 clkout (output) <44> <45> <43> <38> <46> <47> <39> <40> <41> <42> a0 to a23 (output) csn (output) rd, iord (output) uwr, lwr, iowr (output) d0 to d15 (i/o) wait (input) bcyst (output)
preliminary data sheet u15390ej1v0ds 30 pd703130 (d) dma flyby transfer timing (sram external i/o transfer) (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns rd low-level width <32> t wrdl (1 + w d + w f + w) t ? 10 ns rd high-level width <33> t wrdh t ? 10 ns delay time from address, csn to rd <34> t dard 0.5t ? 10 ns delay time from rd to address <35> t drda (0.5 + i)t ? 10 ns delay time from rd to data output <37> t drdod (0.5 + i)t ? 10 ns wait setup time (to address) <38> t saw note t ? 25 ns wait setup time (to bcyst ) <39> t sbsw note t ? 25 ns wait hold time (from bcyst ) <40> t hbsw note 0ns delay time from address to iowr <41> t dawr 0.5t ? 10 ns address setup time (to iowr ) <42> t sawr (1.5 + w d + w)t ? 10 ns delay time from iowr to address <43> t dwra 0.5t ? 10 ns iowr high-level width <44> t wwrh t ? 10 ns iowr low-level width <45> t wwrl (1 + w d + w)t ? 10 ns w f = 0 0 ns delay time from iowr to rd <48> t dwrrd w f = 1 t ? 10 ns delay time from dmaakm to iowr <49> t ddawr 0.5t ? 10 ns delay time from iowr to dmaakm <50> t dwrda (0.5 + w f )t ? 10 ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0, 3 to 5, m = 0 to 3
preliminary data sheet u15390ej1v0ds 31 pd703130 (d) dma flyby transfer timing (sram external i/o transfer) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero and w f = 0. 2. the broken lines indicate high impedance. 3. n = 0, 3 to 5, m = 0 to 3 clkout (output) t1 tw t2 <33> <32> <35> <34> <48> <50> <49> <43> <42> <41> <44> <45> <37> <38> <24> <24> <25> <25> <40> <39> a0 to a23 (output) csn (output) rd (output) dmaakm (output) iord (output) iowr (output) uwr, lwr (output) d0 to d15 (i/o) wait (input) bcyst (output)
preliminary data sheet u15390ej1v0ds 32 pd703130 (e) dma flyby transfer timing (external i/o sram transfer) (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns iord low-level width <32> t wrdl (1 + w d + w f + w)t ? 10 ns iord high-level width <33> t wrdh t ? 10 ns delay time from address, csn to iord <34> t dard 0.5t ? 10 ns delay time from iord to address <35> t drda (0.5 + i)t ? 10 ns delay time from iord to data output <37> t drdod (0.5 + i)t ? 10 ns wait setup time (to address) <38> t saw note t ? 25 ns wait setup time (to bcyst ) <39> t sbsw note t ? 25 ns wait hold time (from bcyst ) <40> t hbsw note 0ns delay time from address to uwr, lwr <41> t dawr 0.5t ? 10 ns address setup time (to uwr, lwr ) <42> t sawr (1.5 + w d + w)t ? 10 ns delay time from uwr, lwr to address <43> t dwra 0.5t ? 10 ns uwr, lwr high-level width <44> t wwrh t ? 10 ns uwr, lwr low-level width <45> t wwrl (1 + w d + w)t ? 10 ns w f = 0 0 ns delay time from uwr, lwr to iord <48> t dwrrd w f = 1 t ? 10 ns delay time from dmaakm to iord <51> t ddard 0.5t ? 10 ns delay time from iord to dmaakm <52> t drdda 0.5t ? 10 ns note for first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0, 3 to 5, m = 0 to 3
preliminary data sheet u15390ej1v0ds 33 pd703130 (e) dma flyby transfer timing (external i/o sram transfer) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero and w f = 0. 2. the broken lines indicate high impedance. 3. n = 0, 3 to 5, m = 0 to 3 clkout (output) t1 tw t2 <44> <45> <48> <52> <33> <37> <38> <24> <24> <25> <25> <40> <39> <42> <41> <43> <51> <32> <35> <34> a0 to a23 (output) csn (output) uwr, lwr (output) rd (output) dmaakm (output) iowr (output) iord (output) d0 to d15 (i/o) wait (input) bcyst (output)
preliminary data sheet u15390ej1v0ds 34 pd703130 (5) page rom access timing (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout ) <26> t skid 18 ns data input hold time (from clkout ) <27> t hkid 2ns off-page data input setup time (to address) <30> t said (1.5 + w d + w)t ? 28 ns off-page data input setup time (to rd) <31> t srdid (1 + w d + w)t ? 32 ns off-page rd low-level width <32> t wrdl (1 + w d + w)t ? 10 ns rd high-level width <33> t wrdh 0.5t ? 10 ns data input hold time (from rd) <36> t hrdid 0ns delay time from rd to data output <37> t drdod (0.5 + i)t ? 10 ns on-page rd low-level width <53> t wordl (1.5 + w pr + w)t ? 10 ns on-page data input setup time (to address) <54> t soaid (1.5 + w pr + w)t ? 28 ns on-page data input setup time (to rd) <55> t sordid (1.5 + w pr + w)t ? 32 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w d : the number of waits due to the dwc1 and dwc2 registers. 4. w pr : the number of waits due to the prc register. 5. i: the number of idle states that are inserted when a write cycle follows a read cycle. 6. maintain at least one of the data input hold times, t hkid or t hrdid .
preliminary data sheet u15390ej1v0ds 35 pd703130 (5) page rom access timing (2/2) note on-page and off-page addresses are as follows. prc register ma5 ma4 ma3 on-page addresses off-page addresses 0 0 0 a0, a1 a2 to a23 0 0 1 a0 to a2 a3 to a23 0 1 1 a0 to a3 a4 to a23 1 1 1 a0 to a4 a5 to a23 remarks 1. this is the timing for the following case. number of waits due to the dwc1 and dwc2 registers (tdw): 1 number of waits due to the prc register (tprw): 1 2. the broken lines indicate high impedance. 3. n = 0, 3 to 5 clkout (output) on-page address note t1 tdw tw t2 to1 tprw tw to2 <24> <25> <24> <25> <24> <25> <24> <25> <26> <27> <36> <32> <31> <53> <55> <27> <26> <36> <37> <33> <30> <54> off-page address note csn (output) uwr, lwr (output) rd (output) d0 to d15 (i/o) wait (input) bcyst (output)
preliminary data sheet u15390ej1v0ds 36 pd703130 (6) dram access timing (a) read timing (high-speed page dram access, normal access: off-page) (1/3) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout ) <26> t skid 18 ns data input hold time (from clkout ) <27> t hkid 2ns delay time from oe to data output <37> t drdod (0.5 + i)t ? 10 ns row address setup time <56> t asr (0.5 + w rp )t ? 10 ns row address hold time <57> t rah (0.5 + w rh )t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w)t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp )t ? 10 ns ras pulse time <62> t ras (2.5 + w rh + w da + w)t ? 10 ns ras hold time <63> t rsh (1.5 + w da + w)t ? 10 ns column address read time for ras <64> t ral (2 + w da + w)t ? 10 ns cas pulse width <65> t cas (1 + w da + w)t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp )t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w)t ? 10 ns we setup time <68> t rcs (2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh )t ? 10 ns output enable access time <72> t oea (2 + w rp + w rh + w da + w) t ? 28 ns ras access time <73> t rac (2 + w rh + w da + w) t ? 28 ns access time from column address <74> t aa (1.5 + w da + w)t ? 28 ns cas access time <75> t cac (1 + w da + w)t ? 28 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
preliminary data sheet u15390ej1v0ds 37 pd703130 (a) read timing (high-speed page dram access, normal access: off-page) (2/3) parameter symbol condition min. max. unit ras column address delay time <76> t rad (0.5 + w rh )t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh )t ? 10 ns output buffer turn-off delay time (from oe ) <78> t oez 0ns output buffer turn-off delay time (from cas ) <79> t off 0ns remarks 1. t = t cyk 2. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
preliminary data sheet u15390ej1v0ds 38 pd703130 (a) read timing (high-speed page dram access, normal access: off-page) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 3 to 5 trpw trhw t2 t1 tdaw tw t3 <56> <61> <57> <58> <59> <62> <76> <63> <64> <60> <77> <65> <67> <66> <71> <73> <68> <75> <74> <72> <70> <69> <79> <37> <27> <25> <26> <25> <24> <78> <24> clkout (output) a0 to a23 (output) rasn (output) we (output) oe (output) wait (input) d0 to d15 (i/o) ucas (output) lcas (output) row address column address
preliminary data sheet u15390ej1v0ds 39 pd703130 [memo]
preliminary data sheet u15390ej1v0ds 40 pd703130 (b) read timing (high-speed page dram access: on-page) (1/2) parameter symbol condition min. max. unit data input setup time (to clkout ) <26> t skid 18 ns data input hold time (from clkout ) <27> t hkid 2ns delay time from oe to data output <37> t drdod (0.5 + i)t ? 10 ns column address setup time <58> t asc (0.5 + w cp )t ? 10 ns column address hold time <59> t cah (1.5 + w da )t ? 10 ns ras hold time <63> t rsh (1.5 + w da )t ? 10 ns column address read time for ras <64> t ral (2 + w cp + w da )t ? 10 ns cas pulse width <65> t cas (1 + w da )t ? 10 ns we setup time (to cas ) <68> t rcs (1 + w cp )t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch t ? 10 ns output enable access time <72> t oea (1 + w cp + w da )t ? 28 ns access time from column address <74> t aa (1.5 + w cp + w da ) t ? 28 ns cas access time <75> t cac (1 + w da )t ? 28 ns output buffer turn-off delay time (from oe ) <78> t oez 0ns output buffer turn-off delay time (from cas ) <79> t off 0ns access time from cas precharge <80> t acp (2 + w cp + w da )t ? 28 ns cas precharge time <81> t cp (1 + w cp )t ? 10 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da )t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da ) t ? 10 ns remarks 1. t = t cyk 2. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
preliminary data sheet u15390ej1v0ds 41 pd703130 (b) read timing (high-speed page dram access: on-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 3 to 5 tcpw to1 tdaw to2 <58> <59> <63> <64> <83> <65> <81> <82> <68> <75> <72> <26> <79> <37> <74> <80> <27> <78> <70> <69> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) wait (input) column address
preliminary data sheet u15390ej1v0ds 42 pd703130 (c) write timing (high-speed page dram access, normal access: off-page) (1/2) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns row address setup time <56> t asr (0.5 + w rp )t ? 10 ns row address hold time <57> t rah (0.5 + w rh )t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w)t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w)t ? 10 ns ras precharge time <61> t rp (0.5 + w rp )t ? 10 ns ras pulse time <62> t ras (2.5 + w rh + w da + w)t ? 10 ns ras hold time <63> t rsh (1.5 + w da + w)t ? 10 ns column address read time (from ras ) <64> t ral (2 + w da + w)t ? 10 ns cas pulse width <65> t cas (1 + w da + w)t ? 10 ns cas-ras precharge time <66> t crp (1 + w rh )t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w)t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh )t ? 10 ns ras column address delay time <76> t rad (0.5 + w rh )t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh )t ? 10 ns we setup time (to cas ) <84> t wcs (1 + w rp + w rh )t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da + w)t ? 10 ns data setup time (to cas ) <86> t ds (1.5 + w rp + w rh ) t ? 10 ns data hold time (from cas ) <87> t dh (1.5 + w da + w)t ? 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
preliminary data sheet u15390ej1v0ds 43 pd703130 (c) write timing (high-speed page dram access, normal access: off-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 3 to 5 trpw trhw t2 t1 tdaw tw t3 <56> <61> <57> <58> <59> <62> <76> <63> <64> <60> <77> <65> <67> <66> <71> <84> <25> <25> <24> <24> <85> <86> <87> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) wait (input) row address column address
preliminary data sheet u15390ej1v0ds 44 pd703130 (d) write timing (high-speed page dram access: on-page) (1/2) parameter symbol condition min. max. unit column address setup time <58> t asc (0.5 + w cp )t ? 10 ns column address hold time <59> t cah (1.5 + w da )t ? 10 ns ras hold time <63> t rsh (1.5 + w da )t ? 10 ns column address read time (from ras ) <64> t ral (2 + w cp + w da )t ? 10 ns cas pulse width <65> t cas (1 + w da )t ? 10 ns cas precharge time <81> t cp (1 + w cp )t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da )t ? 10 ns we setup time (to cas ) <84> t wcs w cp 1w cp t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da )t ? 10 ns data setup time (to cas ) <86> t ds (0.5 + w cp )t ? 10 ns data hold time (from cas ) <87> t dh (1.5 + w da )t ? 10 ns we read time (from ras ) <88> t rwl w cp = 0 (1.5 + w da )t ? 10 ns we read time (from cas ) <89> t cwl w cp = 0 (1 + w da )t ? 10 ns data setup time (to we ) <90> t dswe w cp = 0 0.5t ? 10 ns data hold time (from we ) <91> t dhwe w cp = 0 (1.5 + w da )t ? 10 ns we pulse width <92> t wp w cp = 0 (1 + w da )t ? 10 ns remarks 1. t = t cyk 2. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
preliminary data sheet u15390ej1v0ds 45 pd703130 (d) write timing (high-speed page dram access: on-page) (2/2) tcpw to1 tdaw to2 <58> <59> <63> <64> <83> <81> <65> <89> <88> <84> <85> <92> <91> <86> <87> <90> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) oe (output) we (output) d0 to d15 (i/o) wait (input) column address remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the cpcxx bit of the drcn register (tcpw ): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 3 to 5
preliminary data sheet u15390ej1v0ds 46 pd703130 (e) read timing (edo dram) (1/3) parameter symbol condition min. max. unit data input setup time (to clkout ) <26> t skid 18 ns data input hold time (from clkout ) <27> t hkid 2ns delay time from oe to data output <37> t drdod (0.5 + i)t ? 10 ns row address setup time <56> t asr (0.5 + w rp )t ? 10 ns row address hold time <57> t rah (0.5 + w rh )t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (0.5 + w da )t ? 10 ns ras precharge time <61> t rp (0.5 + w rp )t ? 10 ns column address read time (from ras ) <64> t ral (2 + w cp + w da )t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp )t ? 10 ns cas hold time <67> t csh (1.5 + w rh + w da ) t ? 10 ns we setup time (to cas ) <68> t rcs (2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch 1.5t ? 10 ns ras access time <73> t rac (2 + w rh + w da ) t ? 28 ns access time from column address <74> t aa (1.5 + w da )t ? 28 ns cas access time <75> t cac (1 + w da )t ? 28 ns delay time from ras to column address <76> t rad (0.5 + w rh )t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh )t ? 10 ns output buffer turn-off delay time (from oe) <78> t oez 0ns access time from cas precharge <80> t acp (1.5 + w cp + w da ) t ? 28 ns cas precharge time <81> t cp (0.5 + w cp )t ? 10 ns ras hold time for cas precharge <83> t rhcp (2 + w cp + w da )t ? 10 ns read cycle time <93> t hpc (1 + w da + w cp )t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da ) t ? 10 ns cas pulse width <95> t hcas (0.5 + w da )t ? 10 ns off-page <96> t och1 (2 + w rh + w da )t ? 10 ns cas hold time from oe on-page <97> t och2 (0.5 + w da )t ? 10 ns data input hold time (from cas ) <98> t dhc 0ns remarks 1. t = t cyk 2. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
preliminary data sheet u15390ej1v0ds 47 pd703130 (e) read timing (edo dram) (2/3) parameter symbol condition min. max. unit off-page <99> t oea1 (2 + w rp + w rh + w da )t ? 28 ns output enable access time on-page <100> t oea2 (1 + w cp + w da ) t ? 28 ns remarks 1. t = t cyk 2. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
preliminary data sheet u15390ej1v0ds 48 pd703130 (e) read timing (edo dram) (3/3) note for on-page access from another cycle during the rasn low-level signal. remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 2. the broken lines indicate high impedance. 3. n = 3 to 5 trpw t1 trhw t2 tdaw tcpw tb tdaw te <56> <57> <59> <58> <76> <64> <94> <61> <67> <83> <77> <95> <81> <75> <66> <93> <95> <80> <97> <74> <27> <78> data <74> data <70> <69> <68> <96> <100> <26> <37> <27> <98> <26> <75> <73> <99> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) bcyst (output) wait (input) row address column address column address note
preliminary data sheet u15390ej1v0ds 49 pd703130 [memo]
preliminary data sheet u15390ej1v0ds 50 pd703130 (f) write timing (edo dram) (1/2) parameter symbol condition min. max. unit row address setup time <56> t asr (0.5 + w rp )t ? 10 ns row address hold time <57> t rah (0.5 + w rh )t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (0.5 + w da )t ? 10 ns ras precharge time <61> t rp (0.5 + w rp )t ? 10 ns ras hold time <63> t rsh (1.5 + w da )t ? 10 ns column address read time (from ras ) <64> t ral (2 + w cp + w da )t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp )t ? 10 ns cas hold time <67> t csh (1.5 + w rh + w da ) t ? 10 ns delay time from ras to column address <76> t rad (0.5 + w rh )t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh )t ? 10 ns cas precharge time <81> t cp (0.5 + w cp )t ? 10 ns ras hold time for cas precharge <83> t rhcp (2 + w cp + w da )t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da )t ? 10 ns data hold time (from cas ) <87> t dh (0.5 + w da )t ? 10 ns we read time (from ras ) on-page <88> t rwl w cp = 0 (1.5 + w da )t ? 10 ns we read time (from cas ) on-page <89> t cwl w cp = 0 (0.5 + w da )t ? 10 ns we pulse width on-page <92> t wp w cp = 0 (1 + w da )t ? 10 ns write cycle time <93> t hpc (1 + w da + w cp )t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da ) t ? 10 ns cas pulse width <95> t hcas (0.5 + w da )t ? 10 ns off-page <101> t wcs1 (1 + w rp + w rh ) t ? 10 ns we setup time (to cas ) on-page <102> t wcs2 w cp 1w cp t ? 10 ns off-page <103> t ds1 (1.5 + w rp + w rh ) t ? 10 ns data setup time (to cas ) on-page <104> t ds2 (0.5 + w cp )t ? 10 ns remarks 1. t = t cyk 2. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
preliminary data sheet u15390ej1v0ds 51 pd703130 (f) write timing (edo dram) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 2. the broken lines indicate high impedance. 3. n = 3 to 5 trpw t1 trhw t2 tdaw tcpw tb tdaw te <56> <57> <59> <58> <58> <59> <76> <64> <94> <61> <67> <83> <77> <95> <81> <63> <66> <93> <95> <89> <88> <102> <101> <92> <85> <85> <103> <87> <104> <87> data data clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) we (output) d0 to d15 (i/o) bcyst (output) wait (input) row address column address column address
preliminary data sheet u15390ej1v0ds 52 pd703130 (g) dma flyby transfer timing (dram (edo, high-speed page) external i/o transfer) (1/3) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns delay time from oe to data output <37> t drdod (0.5 + i)t ? 10 ns delay time from address to iowr <41> t dawr (0.5 + w rp )t ? 10 ns address setup time (to iowr ) <42> t sawr (2 + w rp + w rh + w da + w)t ? 10 ns delay time from iowr to address <43> t dwra 0.5t ? 10 ns w f = 0 0 ns delay time from iowr to rd <48> t dwrrd w f = 1 t ? 10 ns iowr low-level width <50> t wwrl (2 + w rh + w da + w)t ? 10 ns row address setup time <56> t asr (0.5 + w rp )t ? 10 ns row address hold time <57> t rah (0.5 + w rh )t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w f + w)t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w f + w)t ? 10 ns ras precharge time <61> t rp (0.5 + w rp )t ? 10 ns ras hold time <63> t rsh (1.5 + w da + w f + w)t ? 10 ns column address read time for ras <64> t ral (2 + w cp + w da + w f + w)t ? 10 ns cas pulse width <65> t cas (1 + w da + w f + w)t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp )t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w f + w) t ? 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5 .w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
preliminary data sheet u15390ej1v0ds 53 pd703130 (g) dma flyby transfer timing (dram (edo, high-speed page) external i/o transfer) (2/3) parameter symbol condition min. max. unit we setup time (to cas ) <68> t rcs (2 + w rp + w rh )t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch 1.5t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh )t ? 10 ns delay time from ras to column address <76> t rad (0.5 + w rh )t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh )t ? 10 ns output buffer turn-off delay time (from oe ) <78> t oez 0ns output buffer turn-off delay time (from cas ) <79> t off 0ns cas precharge time <81> t cp (0.5 + w cp )t ? 10 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da + w f + w) t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da + w f + w) t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da + w f + w)t ? 10 ns off-page <96> t och1 (2.5 + w rp + w rh + w da + w f + w)t ? 10 ns cas hold time from oe (from cas ) on-page <97> t och2 (1.5 + w cp + w da + w f + w) t ? 10 ns delay time from dmaakm to cas <105> t ddacs (1.5 + w rh )t ? 10 ns delay time from iowr to cas <106> t drdcs (1 + w rh )t ? 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. m = 0 to 3
preliminary data sheet u15390ej1v0ds 54 pd703130 (g) dma flyby transfer timing (dram (edo, high-speed page) external i/o transfer) (3/3) trpw t1 trhw t2 tdaw tw t3 tcpw to1 to2 tw tdaw <56> <57> <58> <59> <76> <61> <60> <94> <64> <77> <65> <83> <63> <81> <67> <66> <71> <82> <96> <105> <68> <69> <70> <79> <48> <97> <106> <42> <41> <50> <43> <78> <37> <24> <25> <24> <25> <25> <24> data data clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) dmaakm (output) we (output) iord (output) iowr (output) d0 to d15 (i/o) wait (input) bcyst (output) row address column address column address remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits that are inserted for a source-side access during a dma flyby transfer: 0 2. the broken lines indicate high impedance. 3. n = 3 to 5, m = 0 to 3
preliminary data sheet u15390ej1v0ds 55 pd703130 (h) dma flyby transfer timing (external i/o dram (edo, high-speed page) transfer) (1/3) parameter symbol condition min. max. unit wait setup time (to clkout ) <24> t swk 15 ns wait hold time (from clkout ) <25> t hkw 2ns iord low-level width <32> t wrdl (2 + w rh + w da + w f + w)t ? 10 ns iord high-level width <33> t wrdh t ? 10 ns delay time from address to iord <34> t dard 0.5t ? 10 ns delay time from iord to address <35> t drda (0.5 + i)t ? 10 ns row address setup time <56> t asr (0.5 + w rp )t ? 10 ns row address hold time <57> t rah (0.5 + w rh )t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w f )t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w f + w)t ? 10 ns ras precharge time <61> t rp (0.5 + w rp )t ? 10 ns ras hold time <63> t rsh (1.5 + w da + w f )t ? 10 ns column address read time for ras <64> t ral (2 + w cp + w da + w f + w)t ? 10 ns cas pulse width <65> t cas (1 + w da + w f )t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp )t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w f + w)t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh + w)t ? 10 ns delay time from ras to column address <76> t rad (0.5 + w rh )t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh + w)t ? 10 ns cas precharge time <81> t cp (0.5 + w cp + w)t ? 10 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da + w f + w)t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da + w)t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da )t ? 10 ns we read time (from ras ) <88> t rwl w cp = 0 (1.5 + w da + w)t ? 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
preliminary data sheet u15390ej1v0ds 56 pd703130 (h) dma flyby transfer timing (external i/o dram (edo, high-speed page) transfer) (2/3) parameter symbol condition min. max. unit we read time (from cas ) <89> t cwl w cp = 0 (1 + w da + w)t ? 10 ns we pulse width <92> t wp w cp = 0 (1 + w da + w)t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da + w f + w)t ? 10 ns off-page <101> t wcs1 w cp = 0 (1 + w rh + w rp + w)t ? 10 ns we setup time (to cas ) on-page <102> t wcs2 w cp 1w cp t ? 10 ns delay time from dmaakm to cas <105> t ddacs (1.5 + w rh + w)t ? 10 ns delay time from iord to cas <106> t drdcs (1 + w rh + w)t ? 10 ns delay time from we to iord <107> t dwerd w f = 0 0 ns w f = 1 t ? 10 ns remarks 1. t = t cyk 2. w: the number of waits due to wait. 3. w rh : the number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. w da : the number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. w rp : the number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. w cp : the number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. w f : the number of waits that are inserted for a source-side access during a dma flyby transfer. 8. m = 0 to 3
preliminary data sheet u15390ej1v0ds 57 pd703130 (h) dma flyby transfer timing (external i/o dram (edo, high-speed page) transfer) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits that are inserted for a source-side access during a dma flyby transfer: 0 2. the broken lines indicate high impedance. 3. n = 3 to 5, m = 0 to 3 trpw t1 trhw tw t2 tdaw t3 tcpw tw to2 tdaw to1 <56> <57> <58> <76> <61> <60> <94> <64> <77> <65> <63> <81> <67> <66> <71> <82> <101> <105> <83> <85> <89> <106> <34> <107> <33> <24> <25> <24> <25> <24> data data <59> <88> <102> <92> <35> <32> <25> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) dmaakm (output) we (output) iowr (output) iord (output) d0 to d15 (i/o) wait (input) bcyst (output) row address column address column address
preliminary data sheet u15390ej1v0ds 58 pd703130 (i) cbr refresh timing parameter symbol condition min. max. unit ras precharge time <61> t rp (1.5 + w rrw )t ? 10 ns ras pulse width <62> t ras (1.5 + w rcw note )t ? 10 ns cas hold time <108> t chr (1.5 + w rcw note )t ? 10 ns ras precharge cas hold time <110> t rpc (0.5 + w rrw )t ? 10 ns cas setup time <113> t csr t ? 10 ns note at least one clock cycle is inserted by default for w rcw regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. t = t cyk 2. w rrw : the number of waits due to the rrw0 and rrw1 bits of the rwc register. 3. w rcw : the number of waits due to the rcw0 to rcw2 bits of the rwc register. note this trcw is always inserted regardless of the settings of the rcw0 to rcw2 bits of the rwc register. remarks 1. this is the timing for the following case. number of waits due to the rrw0 and rrw1 bits of the rwc register (trrw): 1 number of waits due to the rcw0 to rcw2 bits of the rwc register (trcw): 2 2. n = 3 to 5 ti t3 trcw trcw note t2 t1 trrw rasn (output) <62> ucas (output) <108> <110> <61> <113> <110> lcas (output) clkout (output)
preliminary data sheet u15390ej1v0ds 59 pd703130 (j) cbr self-refresh timing parameter symbol condition min. max. unit cas hold time <114> t chs ? 5ns ras precharge time <115> t rps (1 + 2w srw )t ? 10 ns remarks 1. t = t cyk 2. w srw : the number of waits due to the srw0 to srw2 bits of the rwc register. remarks 1. this is the timing for the following case. number of waits due to the rrw0 and rrw1 bits of the rwc register (trrw): 1 number of waits due to the rcw0 to rcw2 bits of the rwc register (trcw): 1 number of waits due to the srw0 to srw2 bits of the rwc register (tsrw): 2 2. the broken lines indicate high impedance. 3. n = 3 to 5 th th th trrw tsrw ti th trcw tsrw output signals other than above <115> <114> clkout (output) rasn (output) ucas (output) lcas (output)
preliminary data sheet u15390ej1v0ds 60 pd703130 (7) dmac timing parameter symbol condition min. max. unit dmarqn setup time (to clkout ) <116> t sdrk 15 ns <117> t hkdr1 2ns dmarqn hold time (from clkout ) <118> t hkdr2 until dmaakn ns dmaakn output delay time (from clkout ) <119> t dkda 210ns dmaakn output hold time (from clkout ) <120> t hkda 210ns tcn output delay time (from clkout ) <121> t dktc 210ns tcn output hold time (from clkout ) <122> t hktc 210ns remark n = 0 to 3 remark n = 0 to 3 <121> dmarqn (input) dmaakn (output) tcn (output) <122> <120> <119> <118> <117> <116> <116> clkout (output)
preliminary data sheet u15390ej1v0ds 61 pd703130 [memo]
preliminary data sheet u15390ej1v0ds 62 pd703130 (8) bus hold timing (1/2) parameter symbol condition min. max. unit hldrq setup time (to clkout ) <123> t shrk 15 ns hldrq hold time (from clkout ) <124> t hkhr 2ns delay time from clkout to hldak <125> t dkha 210ns hldrq high-level width <126> t whqh t + 17 ns hldak low-level width <127> t whal t ? 8 ns delay time from clkout to bus float <128> t dkcf 10 ns delay time from hldak to bus output <129> t dhac 0ns delay time from hldrq to hldak <130> t dhqha1 2.5t ns delay time from hldrq to hldak <131> t dhqha2 0.5t 1.5t ns remark t = t cyk
preliminary data sheet u15390ej1v0ds 63 pd703130 (8) bus hold timing (2/2) t1 t2 t3 ti th th th ti t1 a0 to a23 (output) d0 to d15 (i/o) <123> <124> <124> <123> <123> <123> <126> <130> <125> <127> <125> <128> <129> <131> address undefined data clkout (output) hldrq (input) hldak (output) csn/rasm (output) bcyst (output) rd (output) we (output) wait (input) ucas (output) lcas (output) remarks 1. the broken lines indicate high impedance. 2. n = 0, 3 to 5, m = 3 to 5
preliminary data sheet u15390ej1v0ds 64 pd703130 (9) interrupt timing parameter symbol condition min. max. unit nmi high-level width <132> t wnih 500 ns nmi low-level width <133> t wnil 500 ns intpn high-level width <134> t with 4t + 10 ns intpn low-level width <135> t witl 4t + 10 ns remarks 1. n = 100 to 103, 110 to 113, 130 2. t = t cyk nmi (input) <132> <133> intpn (input) <134> <135> remark n = 100 to 103, 110 to 113, 130 (10) rpu timing parameter symbol condition min. max. unit ti13 high-level width <136> t wtih 3t + 18 ns ti13 low-level width <137> t wtil 3t + 18 ns tclr1n high-level width <138> t wtch 3t + 18 ns tclr1n low-level width <139> t wtcl 3t + 18 ns remarks 1. n = 0 to 2 2. t = t cyk remark n = 0 to 2 ti13 (input) <136> <137> tclr1n (input) <138> <139>
preliminary data sheet u15390ej1v0ds 65 pd703130 (11) uart0, uart1 timing (clock-synchronized or master mode only) parameter symbol condition min. max. unit sckn cycle <140> t cysk0 output 250 ns sckn high-level width <141> t wsk0h output 0.5t cysk0 ? 20 ns sckn low-level width <142> t wsk0l output 0.5t cysk0 ? 20 ns rxdn setup time (to sckn ) <143> t srxsk 30 ns rxdn hold time (from sckn ) <144> t hskrx 0ns txdn output delay time (from sckn ) <145> t dsktx 20 ns txdn output hold time (from sckn ) <146> t hsktx 0.5t cysk0 ? 5 ns remark n = 0, 1 sckn (i/o) <142> <140> <141> rxdn (input) <143> <144> input data txdn (output) <145> output data <146> remarks 1. the broken lines indicate high impedance. 2. n = 0, 1
preliminary data sheet u15390ej1v0ds 66 pd703130 (12) csi0, csi1 timing (a) master mode parameter symbol condition min. max. unit sckn cycle <147> t cysk1 output 100 ns sckn high-level width <148> t wsk1h output 0.5t cysk1 ? 20 ns sckn low-level width <149> t wsk1l output 0.5t cysk1 ? 20 ns sin setup time (to sckn ) <150> t ssisk 30 ns sin hold time (from sckn ) <151> t hsksi 0ns son output delay time (from sckn ) <152> t dskso 20 ns son output hold time (from sckn ) <153> t hskso 0.5t cysk1 ? 5 ns remark n = 0, 1 (b) slave mode parameter symbol condition min. max. unit sckn cycle <147> t cysk1 input 100 ns sckn high-level width <148> t wsk1h input 30 ns sckn low-level width <149> t wsk1l input 30 ns sin setup time (to sckn ) <150> t ssisk 10 ns sin hold time (from sckn ) <151> t hsksi 10 ns son output delay time (from sckn ) <152> t dskso 30 ns son output hold time (from sckn ) <153> t hskso t wsk1h ns remark n = 0, 1 sckn (i/o) <149> <147> <148> sln (input) <150> <151> input data son (output) <152> output data <153> remarks 1. the broken lines indicate high impedance. 2. n = 0, 1
preliminary data sheet u15390ej1v0ds 67 pd703130 a/d converter characteristics ( t a = ?40 to +85 c, v dd = cv dd = 3.0 to 3.6 v, hv dd = 5.0 v 10%, v ss = 0 v, hv dd ? 0.5 v av dd hv dd , output pin load capacitance: c l = 50 pf) parameter symbol condition min. typ. max. unit resolution ? 10 bit overall error ? 4lsb quantization error ? 1/2 lsb conversion time t conv 510 s sampling time t samp conversion clock note /6 ns zero scale error ? 4lsb scale error ? 4lsb linearity error ? 3lsb analog input voltage v ian ? 0.3 av ref + 0.3 v analog input resistance r an 2m ? av ref input voltage av ref av ref = av dd 4.5 5.5 v av ref input current ai ref 2.0 ma av dd current ai dd 6ma note conversion clock is the number of clocks set by the adm1 register.
preliminary data sheet u15390ej1v0ds 68 pd703130 4. package drawing 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
preliminary data sheet u15390ej1v0ds 69 pd703130 5. recommended soldering conditions tbd
preliminary data sheet u15390ej1v0ds 70 pd703130 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. reference materials electrical characteristics for microcomputer (u15170j note ) note this document number is that of japanese version. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850e/ms1, v850e/ms2, and v850 family are trademarks of nec corporation.
preliminary data sheet u15390ej1v0ds 71 pd703130 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
pd703130 ? ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8

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